Yang, Xiaohan, Adeyemo, Adedotun, Bala, Anu ORCID: https://orcid.org/0009-0000-6242-5248 and Jabir, Abusaleh (2017) Parasitic effects on memristive logic architecture. In: 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS). IEEE

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Abstract

The most of the memristor based applications which have been proposed so far have not considered the parasitic components. In this paper, we apply a generic memristor model which includes the parasitic effects to our proposed memristive logic architectures. First, we show that the current response of the memristor has the decaying oscillation when the unit step function is applied. Then we demonstrated that our specific memristive logic structure can almost eliminate those effects which are generated by the parasitic components of the memristor. In addition, the propagation delay and the variation of the memristive XOR gate are increased because of the parasitic components. With the delay analysis on cascaded memristive logic design, the experimental results show that our 3T-4M memristive XOR architecture can build the more robust delay based memristive physical unclonable function (PUF) comparing to the existing memristive PUF.

Item Type:	Book Section
Status:	Published
DOI:	10.1109/patmos.2017.8106983
Subjects:	T Technology > T Technology (General)
School/Department:	London Campus
URI:	https://ray.yorksj.ac.uk/id/eprint/13541

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