Yang, Xiaohan, Adeyemo, Adedotun, Bala, Anu ORCID: https://orcid.org/0009-0000-6242-5248 and Jabir, Abusaleh (2016) Novel memristive logic architectures. In: 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). IEEE

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Abstract

We present techniques for realising reliable logic functions and more complex systems based on the switching characteristics of memristors. First we show that memristors have inherent properties for representing multiple valued MIN-MAX logic over the post algebra. We also present efficient architectures for realising multifunction logic gates, and present a technique with hybrid 1T-4M architecture for seamless integration with existing CMOS logic. Memristors have tremendous potential for security aware hardware synthesis. To this end, we present design methods for realising highly efficient Galois Field circuits, which are widely used in crypto hardware, based on our 1T-4M architectures. Experimental results show that our proposed design requires significantly lower power while maintaining reliable operations at high frequencies compared to the CMOS counterparts.

Item Type:	Book Section
Status:	Published
DOI:	10.1109/patmos.2016.7833687
Subjects:	T Technology > T Technology (General)
School/Department:	London Campus
URI:	https://ray.yorksj.ac.uk/id/eprint/13544

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